Job Title. Senior / Principal Analog High-Speed Design Engineer (TSMC N3). Location. Job Summary. We are seeking a highly experienced. Analog High-Speed Design Engineer. with. hands-on TSMC N3 (3nm) FinFET experience. to architect, design, and validate next-generation high-speed analog and mixed-signal IP. This role focuses on. advanced SerDes, clocking, PHYs, and high-speed I/O circuits. in ultra-advanced process nodes, working closely with layo...
I’m looking for Senior Mechanical Engineers with experience in electronics packaging design (ideally with expertise in space, vibration, thermal management, PCB/A, metal enclosures). Essential Duties and Responsibilities. In this position, you will own the complete lifecycle of space hardware from initial electrical/RF design concept to production & unit delivery. Perform mechanical analyses (vibration, thermal, radiation) on new product designs ...
Job Summary. We are seeking a Mechanical Engineer to join our Test Hardware Development team. In this role, you will design, analyze, and validate mechanical structures that support high-performance electronic test systems, including circuit boards, stiffening frames, and miscellaneous support brackets. The ideal candidate has experience with board-level mechanical standard and structural reinforcement methods. Key Responsibilities. Design and de...
Must have Active Secret Clearance. BSEE or BSCS, or equivalent. MSEE preferred. Candidate must be a U.S. citizen and able to qualify for DoD security clearance. 10 years of experience in a design engineering role focusing on functional verification. 10 years of ASIC/FPGA verification experience using SystemVerilog / UVM. Must have experience in: Developing verification plans Designing and implementing SystemVerilog / UVM test benches for constrai...
Role Summary. In this role, you’ll be tasked with assessing and improving Xilinx-based FPGA emulation of Iontra ASIC. You will review the current FPGA build environment, design constraints, and build/timing/utilization reports, and identify improvements and work with Design team to implement improvements to enable complete, accurate, functional, and stable builds on FPGA hardware. What You’ll Be Doing. Review current FPGA build environment, desig...
Overview. We are seeking a driven and resourceful. Recruiter. to join our growing team. The ideal candidate will excel at sourcing, engaging, and placing top-tier talent while building strong relationships with both candidates and hiring managers. This role requires a proactive, organized, and people-focused approach to full-cycle recruiting. The Recruiter will play a vital role in our organization's success by ensuring high-quality hires, mainta...
Role Overview. This Floorplanning Engineer role focuses on chip-level physical architecture and integration for advanced ASICs in deep sub-micron technologies. The position provides hands-on experience with the latest 3 nm and smaller process nodes, defining and optimizing the overall die layout, including partitioning, hierarchy, and placement of major functional blocks, memories, and I/O structures for AI, computing, and networking SoCs. Key Re...
Job Overview. Based in Moorestown, New Jersey, we are a fabless semiconductor company that specializes in RF and millimeter-wave technologies. Our mission is to deliver cutting-edge radio frequency integrated solutions for emerging defense, 5G/6G, and satellite communication applications. As a small and expanding company, we focus on developing high-performance, wideband chips and system-on-chip (SoC) solutions. We are seeking an energetic and te...
Top skills from manager. Recent Tessent experience (especially with SSN – Scan Stream Network). Hands-on DFT Verification experience (not insertion). Full-chip experience (not just block-level). Multi-die experience (highly preferred). Key Responsibilities. Perform DFT verification using Mentor Tessent (LogicBIST, MBIST, SSN). Verify scan structures and test logic at the full-chip and multi-die level. Collaborate with design and DFT teams to ensu...
As discussed on the call, I’m sharing the DV requirements below. Please send resumes of suitable candidates. along with a brief 3–4 lines summary for each profile when you attach them. Once we review the resumes, we can begin scheduling interviews starting next week. We already emphasized that we’re looking for strong SoC DV candidates. System-level experience is highly preferred. Familiarity with PCIe, HBM, Ethernet, or D2D is a plus. Here’s a g...
