Field-Programmable Gate Arrays Engineer

Must have Active Secret Clearance

• BSEE or BSCS, or equivalent; MSEE preferred
• Candidate must be a U.S. citizen and able to qualify for DoD security clearance
• 10 years of experience in a design engineering role focusing on functional verification
• 10 years of ASIC/FPGA verification experience using SystemVerilog / UVM
• Must have experience in: Developing verification plans Designing and implementing SystemVerilog / UVM test benches for constrained-random verification Developing functional coverage models Writing and debugging directed and random test cases Enabling test benches for hardware acceleration
• Experience with automation/scripting (Perl, sed, awk, tcl/tk, sh)
• C programming desirable. SystemC and C used in conjunction with chip design and verification highly desired
• Good communication skills
• Experience with Formal verification / property checking is a plus
• Experience with emulation or FPGA prototyping is a plus
• RTL design experience and knowledge of standard protocols (such as PCIe) is a plus
• FPGA experience is a plus