DFT Engineer

Top skills from manager:

1. Recent Tessent experience (especially with SSN – Scan Stream Network)
2. Hands-on DFT Verification experience (not insertion)
3. Full-chip experience (not just block-level)
4. Multi-die experience (highly preferred)

Key Responsibilities:

• Perform DFT verification using Mentor Tessent (LogicBIST, MBIST, SSN).
• Verify scan structures and test logic at the full-chip and multi-die level.
• Collaborate with design and DFT teams to ensure coverage, debug, and flow integrity.
• Contribute to validation and bring-up of complex SoCs.

Top Skills manager is looking for:

• Recent Tessent (Siemens/Mentor) hands-on experience (SSN/ Scan Steam Network experience ideal).
• Strong DFT Verification background (not just ATPG/scan).
• Full-chip verification experience.
• Multi-die or chiplet experience preferred.