color:black;mso-ansi-language:EN-US">we are mso-highlight:yellow;mso-ansi-language:EN-US">Looking for someone who has more experience in the DO-254 process FPGA exp

mso-ansi-language:EN-US">Job Description:

mso-ansi-language:EN-US">

color:black;mso-ansi-language:EN-US">1. Must have FPGA design principles. Working with Xilinx/Altera FPGA.
2. Must have done RTL synthesis, constraints design, timing closure
3. Must have experience with design and testing the development to verify the RTL design using Verilog, VHDL, or SV/UVM
4. Must have DO-254 and Aerospace background with SV/UVM skills
5. Must be able to develop Communications and fault logging CPLD/FPGA design.
6. Must have experience in developing PHAC, HDP, Requirements capture, design documentation
7. Must have hands-on experience with Cadence or Synopsys tool, Microsemi Libero, or Xilinx Vivado tool.
8. Familiar with the SCRUM/Sprint JIRA process.