Job Description The Advanced Design Library Technology (ADLT) group plays a leading role in digital logic design pathfinding, definition and development for Intel's next generation technologies. As a Digital Library Vertical Lead, you will be working closely with experts from the ADLT team and partnering organizations in Advanced Design, Design Enablement and Technology Development across the entire digital design stack. Technical work includes device/cell level optimization, standard cell library definition and design, block level PPA implementation and optimization, and Post-Si learning. This is a highly visible technical role with wide exposure and high impact potential across all facets of digital design.Your responsibilities will include:- Interfacing with external customers and partners.- Defining, tracking and coordinating various DTCO (Design-Technology Co-Optimization) activities.- Defining and maintaining technology PPA targets and status.- Defining test chip content and tracking Post-Si status on yield/performance/Vmin.- Defining and developing methodologies to track and report Pre-Si and Post-Si metrics.Candidate must exhibit the following behavioral traits/skills:- Track record of individual technical contributions and/or technical leadership across a team.- Ability to effectively communicate technical results to technical and executive leadership.#DesignEnablementQualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications:Candidate must possess a BS degree with 9 years of experience or MS degree with 6 months of experience or Ph.D. degree with 4 years of experience in Electrical Engineering, Computer Engineering, or related field.6 years of experience in the following:- Digital design in advanced nodes.Preferred Qualifications:8 years of experience in the following:- Standard cell library definition and design .- DTCO in the digital design space.- Optimizations for yield/performance/Vmin improvements.- Test chip definition and Post-Si data analysis.Inside this Business Group As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in theTechnology Development and Manufacturing Groupare part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth. Other Locations US, TX, Austin; US, AZ, Phoenix; US, CA, Folsom; US, CA, Santa Clara Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.Annual Salary Range for jobs which could be performed in US, California: $162,041.00-$259,425.00*Salary range dependent on a number of factors including location and experience Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.#J-18808-Ljbffr

by Jobble