Title: RTL Design Lead

Location: Plymouth, MN or Deer Valley, AZ (Onsite)

Duration: 12 Months Contract

Our client is seeking a senior RTL Design Lead for a long term, onsite contract opening.

Key Responsibilities

• Lead the development of custom radiation hardened DDR3 IP, controller, and PHY.
• Serve as a point of contact for internal and external DDR IP development-related activities.
• Provide technical leadership and guidance to internal and external development teams.
• Ensure compliance with DDR3 requirements and specifications.
• Maintain deep knowledge of DDR protocols, including DMI, and apply this knowledge in development.
• Oversee work on logic design, Clock Domain Crossing (CDC) solutions, and voltage plane optimization.
• Oversee verification processes for DDR IP development

He/She will be using following tools and must posses below experience of tools

1. RTL Compiler

2. Design Compiler

3. ASIC synthesis tools like DC, Genus

4. FPGA tool platform

5. CDC tools

Required Experience

• Experience in DDR IP development
• Familiarity with logic design, CDC solutions, and voltage plane optimization.
• Familiarity with verification concepts in DDR IP development.
• Familiarity with analog circuit development, with a focus on IO circuitry and PHY development.
• Strategic awareness of the competitive landscape for DDR IP.
• Radiation effects analysis knowledge/experience
• Advanced node and SOI technology design experience
• Knowledge of OS Linux, scripting languages e.g., Perl, Shell, TCL
• Laboratory experience (hardware configuration, measurement systems)
• Excellent communication and teamwork skills.
• Bachelor's or higher degree in Electrical Engineering, Computer Science, or a related field.
• ship is required with no known barriers to achieve a USG Secret security (no dual citizenships)