You haven't searched anything yet.
Job Description
We are looking for a hands-on Senior Digital Design Engineering Manager to drive high-speed connectivity solutions. You will build and lead a team that will deliver micro-architecture and implementation of the front-end digital design, including RTL, synthesis, IP integration, and block-level verification for high performance ASICs. The candidate must have good knowledge of communication/interface protocols such as CXL/PCIE (Gen-3 and above) or Ethernet.
Basic qualifications:
Required experience:
Preferred experience:
The base salary range is USD 192,000.00 USD – USD 260,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
Full Time
$207k-233k (estimate)
01/13/2024
07/10/2024
asteralabs.com
Santa Clara, CA
<25