Mixed-Signal Design Verification Manager -10286

Senior Mixed-Signal Design Verification Manager

Experience Level: Management

Job Type: Regular

Location: Richardson, TX

Travel: 10% or less, domestic or international

Role Summary

Lead and develop a team of verification engineers responsible for top-level design verification of mixed-signal and power-management integrated circuits (ICs). Drive verification strategy, technical excellence, automation, and collaboration across design and test teams to deliver high-quality, reliable semiconductor products.

Key Responsibilities

• Manage, mentor, and grow verification engineers across experience levels.
• Define technical direction and verification strategies.
• Lead customer-focused verification for motor drivers, power-loss protection, point-of-load, and battery-management ICs.
• Develop and execute metric-driven verification plans based on functional, performance, and test specifications.
• Create constrained-random tests and automated checkers using UVM.
• Develop accurate real-number models (RNM) and Verilog-AMS models for top-level simulations.
• Collaborate with design teams to debug and resolve verification issues.
• Partner with design and test teams to improve first-pass silicon testability.
• Improve verification methodologies using industry best practices.
• Automate verification workflows and repetitive tasks.

Required Qualifications

• Bachelor’s degree in Electrical Engineering or a related field, emphasizing mixed-signal design and verification.
• 15 years of relevant experience, or equivalent advanced education and experience, in analog/mixed-signal design or verification of analog and power-management ICs.
• Experience managing a team or serving as a functional team lead.
• Hands-on expertise in UVM, analog and digital design fundamentals, and power-management systems.
• Strong problem-solving, debugging, communication, and collaboration skills.
• Expertise in mixed-signal simulation, including SPICE/Spectre, event-based simulators, co-simulation environments, simulation debugging, and silicon debugging.

Preferred Qualifications

• Master’s degree in Electrical Engineering or a related field.
• Experience with top-down design methodology.
• Proficiency in shell scripting or Python.
• Familiarity with SV-UDN/EENET modeling techniques.
• Experience with GUI-based and command-line simulation workflows.
• Proficiency in SystemVerilog assertions and functional coverage.
• Understanding of AI integration into verification workflows.