Job Title: Sr. Coherent Designer

Location: Austin Texas

Duration: 6 Months (possible extension long term project)

Description

• As a senior designer on coherent interconnect micro-architect, you will be responsible for working on the micro-architecture development of custom coherent interconnect IP and/or last level cache blocks.
• In this role you will be interacting with the system architects, verification, performance/power and design implementation teams.
• You will be owning and driving the critical coherent interconnect related RTL design, performance and power optimization and also work on logic debug and timing closure of the design.
• Solid engineering foundation and RTL design experience are desired for success.
• Help mentor junior engineers in the team.

Key responsibilities include:

• Drive the timely development and debug of new features on custom coherent interconnect IP and/or last level cache [LLC] blocks.
• Working on SOC IP delivery with all sanity checks.
• Work on timing debug and closure.
• Working on LINT, CDC flows and analysis.
• Work on power artist flow and power analysis.
• Working on ECO flows.
• Work with the verification team to verify the functionality and correctness of the design.
• Collaborate with implementation to achieve your timing and area.
• Produce quality RTL on schedule meeting PPA goals
• Engage with performance and power team on achieving performance and power goals.
• Partner with the physical design and CAD team to resolve implementation-level details.

Requirements

• PhD, Master’s Degree or Bachelor’s Degree, Computer Engineer with over 12 years of experience.
• Strong background owning and driving the RTL design of various sub-blocks of interconnect or LLC for high-performance digital designs
• Demonstrated experience of successful architecture through RTL design experience on high-performance digital designs
• Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
• Knowledge of system caches and directory snoop filter protocols.
• Familiarity with different on-chip network topologies: mesh, ring, crossbar.
• Experience in leading and mentoring a team of engineers.
• Knowledge of in Arm AMBA5 CHI, AMBA4 ACE or AXI coherent interconnect and bus protocols
• Knowledge of memory subsystem design including coherent cache design.
• Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team.

The preferred candidate will possess the following:

• Knowledge of Verilog/VHDL, scripting, STA, DFT, ECO flows.
• Proficient in AMBA, ACE, AXI, CHI protocols.
• Knowledge of memory controller and either coherent interconnect or cache design.
• Knowledge of memory subsystem, coherency, and directory snoop filter protocols.
• Familiarity with different on-chip network topologies: mesh, ring, crossbar.
• Experience with a scripting language like Perl or Python'