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Sr. Logic Design Engineer - CPU Microarchitecture (RISC-V)
Theery San Jose, CA
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$111k-127k (estimate)
Full Time 1 Week Ago
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Theery is Hiring a Sr. Logic Design Engineer - CPU Microarchitecture (RISC-V) Near San Jose, CA

Company Overview: We are a leading technology firm at the forefront of innovation in the semiconductor industry. We specialize in cutting-edge CPU design, with a focus on RISC-V architecture. Our team comprises top-tier engineers dedicated to pushing the boundaries of performance, efficiency, and scalability.

Position Overview: We are seeking a skilled Logic Design Engineer with a deep understanding of CPU microarchitecture, particularly within the RISC-V ecosystem. As a crucial member of our team, you will play a pivotal role in designing and implementing next-generation CPU cores, contributing to the advancement of our technology roadmap.

Responsibilities:

  1. Microarchitecture Design: Design and develop high-performance CPU microarchitectures, with a focus on optimizing key metrics such as IPC (Instructions Per Cycle), power efficiency, and area utilization.
  2. RTL Implementation: Translate microarchitectural specifications into RTL (Register Transfer Level) designs using hardware description languages (HDLs) such as Verilog or VHDL.
  3. Performance Analysis: Conduct thorough performance analysis and simulation to validate the functionality and performance of CPU designs under various workloads and operating conditions.
  4. Pipeline Design: Architect and refine instruction pipelines, including instruction fetch, decode, execute, and retire stages, to achieve optimal performance and latency characteristics.
  5. Cache and Memory Subsystem Design: Design and optimize cache hierarchies and memory subsystems to enhance CPU performance, scalability, and efficiency.
  6. Collaboration: Work closely with cross-functional teams, including architecture, verification, and physical design teams, to ensure seamless integration and verification of CPU designs.
  7. RISC-V Expertise: Leverage expertise in the RISC-V instruction set architecture (ISA) to design and implement CPU cores compliant with RISC-V standards.
  8. Innovation: Stay abreast of the latest advancements in CPU microarchitecture, RISC-V, and related technologies, and contribute innovative ideas to enhance the performance and capabilities of our CPU designs.

Qualifications:

  • Bachelor's, Master's, or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field.
  • Solid understanding of computer architecture principles and microarchitecture concepts.
  • Proficiency in hardware description languages (Verilog/VHDL) and experience with RTL design.
  • Hands-on experience with CPU microarchitecture design and optimization.
  • Familiarity with RISC-V architecture and ISA specifications is highly desirable.
  • Strong analytical and problem-solving skills, with a keen attention to detail.
  • Excellent communication and collaboration abilities, with a track record of working effectively in cross-functional teams.
  • Prior experience in the semiconductor industry and familiarity with ASIC design flows is a plus.

Please apply here or send cv directly to Kevin@Theery.com

Job Summary

JOB TYPE

Full Time

SALARY

$111k-127k (estimate)

POST DATE

04/19/2024

EXPIRATION DATE

05/07/2024