Role/ Responsibilities:

• Demonstrate a strong knowledge of all aspects of timing and synthesis for a wide variety of designs.
• Understand crosstalk, noise, OCV, timing margins. Familiarity with Clock specs, jitter, IR drop, spice analysis.
• Working with multi-site teams for execution
• Work with methodology teams to constantly improve flows and processes.
• BS/MS in Electrical or Computer Engineering
• 5-10 years of experience in Static Timing Analysis
• Experience with STA Lead roles.

Skills Required:

Physical Design activities for MCU/MPU SoC's.

• Expertise in developing, implementing, and verifying STA constraints.
• Expertise in efficient closure of Subsystem as well as SoC-level timing including running optimization on PTECO for timing and Power.
• Knowledge of industry standards and practices in Timing closure, Physical Design, Floor-planning, and Place & Route
• Knowledge of basic Architecture and Verilog to collaborate with RTL and IP design teams for timing fixes.
• Contribute to timing flow and methodology improvements.