Description
Be responsible for digital design of image sensor, SoC integration and IP design, analysis, integration, and validation. Work closely with back-end team in floor-planning, timing closure and DFT. Conduct image sensor array/analog related timing control design and STA. Perform chip bring-up, validation and debugging. Design, integrate and validate ISP data pipes according to PRD/design specification and system architecture of SoC CIS products, following ASIC design flow: coding, simulation, synthesis, static timing analysis, formality verification, DFT, using Simvision, EDA tools such as Prime Time, cadence Virtuoso, Design Compiler, Integrator, and Verilog and System Verilog programming languages etc. Conduct design verification and modeling using SVA, Python, Perl, C /SystemC, and HLS. Work with sensor digital and analog engineers for system design, integration and validation. Work with algorithm engineers for module level design, including hardware C model implementation, micro architecture design, RTL design and hardware/software co-simulation. Work with algorithm andapplication engineers for image tuning and qualification. Conduct silicon validation, debugging and tuning.
Master's degree in Electrical Engineering, Computer Engineering or other related fields.
Required Coursework: Digital System Design, VLSI Circuit Design, VLSI System Design, and Computer Systems.
Required skills:

• Programming using in Verilog;
• Computer architecture
• Interface protocols such as AXI and PCIE;
• Logic simulation, C , scripting with python and perl;
• Reading schematics, EDA tools like Virtuoso, design compiler.
• Debug using Simvision

Annual base salary for this role in California, US is expected to be between $126,464 - $130,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.