Position: Senior DFT Engineer
Location: Sunnyvale, CA ( Onsite) 
Status: Full-time (Salary Benefits Bonuses)
Responsibilities:
• Responsible for MBIST Logic Insertion in the RTL for memories
• Responsible for Scan Logic Insertion
• Responsible for pattern generation and validation
• Work with Logic, Verification and PD owners of design blocks to close on the DFT requirements
• Silicon Debug on ATE
Requirements:
Must have experience and knowledge of DFT concepts, including:
• MemoryBIST (MBIST), Logic BIST (LBIST) and Memory Repair
• Scan compression and ATPG generation, Test coverage analysis
• JTAG Boundary Scan
• iJTAG (1687)
• SerDes BIST and IO BIST
• Knowledge of Verilog, RTL coding, and multi-domain clock synchronization
• Must have experience with On Chip clocking
• Experience with Static Timing Analysis constraints at test mode
• Experience with Design Tools, such as simulation, synthesis, waveform viewers, and debugging
• BS (EE or CS) or MS (EE or CS) required with 8 years’ experience with DFT
The anticipated annual base salary for this position is between $130,000 - $180,000 which also includes a comprehensive benefits package.