Recent Searches

You haven't searched anything yet.

8 Principal ASIC Design Engineer Jobs in Sunnyvale, CA

SET JOB ALERT
Details...
Candidate Experience site
Sunnyvale, CA | Full Time
$134k-165k (estimate)
10 Months Ago
SpaceX
Sunnyvale, CA | Full Time
$166k-190k (estimate)
1 Day Ago
SpaceX
Sunnyvale, CA | Full Time
$155k-178k (estimate)
1 Day Ago
Wipro
Sunnyvale, CA | Full Time
$153k-174k (estimate)
1 Week Ago
Fortinet
Sunnyvale, CA | Full Time
$138k-168k (estimate)
2 Months Ago
Apple
Apple
Sunnyvale, CA | Full Time
$100k-120k (estimate)
1 Month Ago
Amazon
Sunnyvale, CA | Full Time
$147k-172k (estimate)
1 Month Ago
Amazon
Sunnyvale, CA | Full Time
$129k-153k (estimate)
2 Months Ago
Principal ASIC Design Engineer
$134k-165k (estimate)
Full Time 10 Months Ago
Save

sadSorry! This job is no longer available. Please explore similar jobs listed on the left.

Candidate Experience site is Hiring a Principal ASIC Design Engineer Near Sunnyvale, CA

Overview

Fortinet is looking for a passionate ASIC Designer to join our R&D team! This role involves working on cutting edge high performance ASIC design from specification to RTL implementation. The new member of our team will have direct involvement in designing complex and innovative technologies. This position offers a large scope of experience and direct involvement with the complex and innovative technology and in addition, there is the opportunity to work alongside a close knit team of seasoned software, hardware and network processor developers.

Job Responsibilities

  • Develop network processing ASIC/FPGA architecture and micro architecture specification
  • Design high performance and high quality ASIC/FPGA design from specification to RTL implementation
  • Perform ASIC/FPGA verification, lint/cdc, synthesis, timing analysis and IP integration
  • Implement network packet processing system using Altera/Xilinx FPGA
  • Participate in system/board level bring up, debugging and support

Experience Required

  • 8 years or more networking or processor design experience
  • Strong track record of ASIC/FPGA design from concept to mass production
  • Hands on experience in Verilog HDL coding and verification
  • Experience of high performance ASIC/FPGA design from specification to system bring up
  • Experience with Altera/Xilinx FPGA architecture, tools and IP portfolio
  • Ethernet and TCP/IP networking concept and protocols knowledge
  • Knowledge of System Verilog and UVM verification methodology
  • Highly motivated, positive, detail oriented and responsible
  • Good team player and good communication skills

Educational Requirement

  • MSEE/MSCS

The US base salary range for this full-time position is $160,000-$220,000. Fortinet offers employees a variety of benefits, including medical, dental, vision, life and disability insurance, 401(k), 11 paid holidays, vacation time, and sick time as well as a comprehensive leave program.

Wage ranges are based on various factors including the labor market, job type, and job level. Exact salary offers will be determined by factors such as the candidate's subject knowledge, skill level, qualifications, experience, and geographic location.

All roles are eligible to participate in the Fortinet equity program, Bonus eligibility is reviewed at time of hire and annually at the Company’s discretion.

#LI-BHAVYA
#GD

Job Summary

JOB TYPE

Full Time

SALARY

$134k-165k (estimate)

POST DATE

07/04/2023

EXPIRATION DATE

05/11/2024

Show more

Candidate Experience site
Full Time
$134k-169k (estimate)
Just Posted
Candidate Experience site
Full Time
$126k-158k (estimate)
Just Posted