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We are looking for Principal Design Verification Engineers with proven experience in working on industry standard protocols such as PCIe/CXL/DDR/Ethernet. Using your coding and protocol expertise, you will contribute to the functional verification of the designs from coming up with block level and system level verification plan to writing test sequences, test execution, collecting and closing coverage.
Basic qualifications
Required Experience
Preferred Experience
The base salary range is $160,000.00 – $240,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
Full Time
$160k-182k (estimate)
10/04/2023
07/10/2024
asteralabs.com
Santa Clara, CA
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