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We are looking for Principal Design Verification Engineers with a flair for being a code breaker, ability to come up hybrid mechanisms for verification of complex ASICs. Experience with System Verilog, C, C , Python or other scripting languages would be a plus. Using your coding and problem-solving skills, you will contribute to the functional verification of the designs. You'll be responsible for the full life cycle of verification, from planning to writing tests to debugging, collect and closing coverage. You’ll also work with the software and system validation teams to come up with test plans and executing them in emulation platforms.
Basic qualifications
Required Experience
Preferred Experience
The base salary range is USD 170,000.00 – USD 250,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
Full Time
$89k-106k (estimate)
09/20/2023
05/13/2024
asteralabs.com
Santa Clara, CA
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