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Principal System Validation Engineer
Astera Labs Santa Clara, CA
$69k-93k (estimate)
Full Time 2 Months Ago
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Astera Labs is Hiring a Principal System Validation Engineer Near Santa Clara, CA

Job Description

  • Develop and perform system validation tests using leading-edge Data Center equipment and scalable automation platforms. The validation team holds customers’ system requirements in the highest regard and is solely responsible for certifying a product’s conformance to this high bar.
  • Understand the performance and functionality requirements our ICs must deliver to enable customers developing Data Center systems using Astera Labs’ game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications.
  • Formulate a comprehensive validation plan, automate the testing of ICs and board products in a data-centric manner, design experiments to root-cause unexpected behavior, report results and specification compliance in an automated fashion
  • Work with key customers directly to understand their care-abouts and highlight the unique capabilities and performance of Astera Labs’ solutions.

Education and Experience Requirements

  • Strong academic and technical background in electrical or computer engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred.
  • ≥8 years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.

Desired qualifications

  • Strong knowledge in scripting for automation of validation efforts (e.g. Python, Matlab)
  • Experience with silicon bring-up, debugging complex electrical and system performance issues, production ramp.
  • Very knowledgeable about common high-speed SerDes protocols like Ethernet, PCIe etc., and the electrical, system level specifications defined in the standard documents (IEEE802.3, PCIe Base Specification etc.)
  • Very knowledgeable about SerDes architecture including Tx/Rx equalization, adaptation, CDR, block level requirements and SerDes link jitter budget.
  • Experience working with lab equipment such as protocol analyzers, BERT, real-time scopes, sampling scopes and VNA
  • Experience with PAM4 SerDes validation
  • Knowledge of schematic capture and PCB layout tools from Cadence, Altium, etc.
  • Knowledge of Signal Integrity simulation tools
  • Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer/internal meetings in advance, and to work with minimal guidance and supervision.
  • Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind!

The base salary range is $180,000.00 USD – $260,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

Job Summary

JOB TYPE

Full Time

SALARY

$69k-93k (estimate)

POST DATE

03/16/2024

EXPIRATION DATE

06/30/2024

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