RTL ASIC Design Engineers with 8 to 15 years of experience.

No of Openings: 2

Sunnyvale, CA

Job Description:

· 8 years of Exp with Logic design /micro-architecture / RTL coding is a must.

· Expertise in Verilog & System Verilog is a must.

· Experience in Synthesis / Understanding of timing concepts for ASIC is required.

· Experience in design of DDR / USB /SATA/ PCIe controller or such complex protocols is a plus.

· Hands on experience in Multi Clock designs, Asynchronous interface is a must.

· Experience on tools utilized in all phases of ASIC development such as Lint, CDC, Simulation etc. is required.

· Knowledge of low power concepts and experience is a plus.