Senior SoC Design Engineer

Job Title: Senior SoC Design Engineer

Location: On Site - San Jose, California, United States

Salary: $180,000-$230,000

Skills: SoC Design, RTL Integration, IP block integration, Scripting (Python/Perl/Tcl), Digital Design (Verilog/SystemVerilog)

About the Technology Company / The Opportunity:

Join a pioneering technology company dedicated to building the infrastructure powering the next decade of AI. Leveraging deep expertise in semiconductors, AI systems, and software innovation, our client is committed to enabling smarter devices and sustainable data centers. As a Senior SoC Design Engineer, you'll collaborate with a world-class team of visionaries and problem-solvers to push the boundaries of AI hardware—making a meaningful, global impact in a fast-growing environment.

Responsibilities:

• Integrate multiple IP blocks and subsystems to develop comprehensive System-on-Chip (SoC) solutions ensuring proper connectivity and signal routing.
• Develop and maintain top-level RTL integration structures including clock, reset, Design for Testability (DFT), power management, and system-level connectivity.
• Collaborate closely with IP design teams to successfully incorporate in-house, commercial, and open-source IP into SoC designs.
• Create and implement detailed test plans for integration, working alongside verification engineers to achieve robust coverage and closure.
• Develop and optimize scripts and automation tools to streamline SoC assembly and integration processes.
• Document integration procedures, generating design specifications, guidelines, and verification reports for engineering teams.
• Partner with Physical Design teams to ensure integration supports efficient place-and-route implementation and timing closure.

Must-Have Skills:

• Bachelor's or Master’s degree in Electrical/Computer Engineering or a related discipline.
• 7 years of hands-on experience in digital design with Verilog or SystemVerilog.
• Proven experience integrating complex SoCs with diverse IP blocks including open source IP, processor cores, AXI/AHB fabric IP, memory controllers, and high-speed interfaces.
• Expertise in designing and integrating infrastructure components such as clock, reset, DFT, monitors, and power management.
• Strong proficiency with scripting languages (Python, Perl, Tcl) for automation and workflow optimization.
• Skilled with EDA tools and simulation environments (ModelSim, VCS, Xcelium) for verification and synthesis.
• Exceptional analytical, communication, and debugging abilities for multi-block integration challenges.

Nice-to-Have Skills:

• Experience integrating open source IP of variable quality into commercial-grade SoCs.
• Knowledge of current AI and edge device requirements as applied to SoC architecture.
• Background in developing and maintaining integration automation frameworks for large-scale semiconductor projects.
• Familiarity with emerging standards in connectivity, power efficiency, and high-speed communication interfaces.
• Exposure to collaborative multi-disciplinary engineering teams across hardware and software domains.