What are the responsibilities and job description for the Senior ASIC Design Verification Engineer position at Talently?
Job Title: Senior ASIC Design Verification Engineer
Location: On Site - San Jose, California, United States
Salary: $200,000-$230,000
Skills: ASIC Design Verification, SystemVerilog/UVM, Chip-level Validation, Test Planning, C/C Programming
About the Technology Company / The Opportunity:
Are you passionate about pushing the boundaries of AI and semiconductor hardware? Our client, a rapidly growing innovator in the technology industry, is shaping the future of AI infrastructure by empowering smarter devices and sustainable data centers. This is an exceptional opportunity for ambitious engineers to work alongside industry-leading experts and play a critical role in bringing next-generation AI hardware to life.
Responsibilities:
- Lead comprehensive verification planning and execution for fabric-level and full-chip ASIC designs, ensuring robust validation across all design hierarchies.
- Collaborate cross-functionally with teams in architecture, firmware, and design to create and refine detailed test plans.
- Design and implement advanced testbenches using constrained random stimulus generation, intelligent checkers, scoreboards, and targeted assertions.
- Architect and execute verification strategies, including coverage analysis, automated regression management, and data-driven insights for high efficiency and quality.
- Drive verification best practices through structured code reviews, agile sprint planning, and systematic feature deployment processes.
- Innovate by researching and adopting next-generation methodologies, automated flows, and emerging technologies, such as AI-driven verification tools.
Must-Have Skills:
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
- 7-10 years of hands-on ASIC/SoC design verification experience, including test plan development, simulation environment creation, and complex debugging.
- Expertise in fabric-level and chip-level verification methodologies and best practices.
- Advanced proficiency with SystemVerilog/Verilog, UVM, and C/C programming, including embedded code for RISC-based processors.
- Proven ability to create scalable verification flows and frameworks, and implement coverage-driven, assertion-based verification strategies.
Nice-to-Have Skills:
- Experience with automated verification flows and AI-driven verification tools.
- Background in deploying verification environments for inference chiplets or AI hardware.
- Familiarity with advanced regression management and coverage analysis tools.
- Strong cross-functional communication skills and previous exposure to fast-paced, agile engineering environments.
- Knowledge of systematic feature deployment and best practices in verification documentation.
Salary : $200,000 - $230,000