What are the responsibilities and job description for the Field-Programmable Gate Arrays Engineer position at Radley James?
A leading quantitative trading firm and early pioneer of hardware-accelerated low-latency systems is seeking an FPGA Engineer to join a high-impact engineering group. This team builds and optimises the hardware that powers real-time strategy execution across global markets. You’ll work closely with quantitative researchers, strategy developers, and traders to design FPGA solutions that directly influence trading performance.
You’ll be involved across the full hardware lifecycle—architecture, RTL design, simulation, testing, and deployment—focusing on accelerating critical data paths and improving interfaces between hardware and software. The environment encourages technical ownership, experimentation, and close collaboration with other specialists across the business.
They are especially interested in talking with candidates who’ve directly worked on programmable logic/custom programable logic.
Key responsibilities include:
• Designing and implementing FPGA architectures for latency-sensitive trading systems
• Translating trading requirements into scalable hardware solutions
• Developing high-speed interfaces and board-level logic for production
• Deploying and iterating on hardware based on real-time performance
• Contributing to simulation, testing, and continuous optimisation
Requirements:
• 8 years of FPGA or ASIC development using VHDL, Verilog, or SystemVerilog
• Experience with high-speed interfaces (Ethernet, PCIe) preferred
• Exposure to C, C#, or Java is a plus
• Degree in EE, CS, Mathematics, or related field
• No finance experience required
This role offers significant technical ownership, meaningful impact on live trading systems, and a collaborative environment focused on high-performance engineering.