IC Package Design Engineer

Piper Companies is looking for a IC Package Design Engineer to join a cutting-edge start up onsite Monday through Friday near San Jose, CA. The ideal IC Package Design Engineer will lead the physical layout of advanced multi-die substrates that integrate multiple chiplets into a high-density, high-performance package.

Responsibilities for the IC Package Design Engineer:

• Lead the physical layout of complex multi-die substrates while supporting chiplet-based integration.
• Collaborate with package integration, signal/power integrity, and mechanical teams to ensure successful layout implementation.
• Drive routing feasibility and co-design alignment with floor planning, mechanical, and system constraints.
• Own the full layout process, ensuring performance, manufacturability, and design quality.
• Use industry-standard tools like Siemens Xpedition and Cadence Allegro APD to execute and refine substrate designs.
  
  

Qualifications for the IC Package Design Engineer:

• 8 years of experience in substrate layout design for advanced packaging.
• Must be eligible to work in the United States and obtain and maintain an Active U.S. Government Secret Clearance.
• Strong background in physical layout and collaboration with ASIC, signal, and power teams.
• Proficient in Siemens Xpedition and Cadence Allegro APD
• Bachelor’s degree in Electrical Engineering preferred.
  
  

Compensation/Benefits for the IC Package Design Engineer:

• Salary Range: $200,000 – $260,000 annually
• Comprehensive Benefits: Medical, Dental, Vision, 401K, PTO, Sick Leave (if required by law), and Holidays
  
  

This job opens for applications on 5/14/2026. Applications for this job will be accepted for at least 30 days from the posting date.

Keywords: Package Layout, Substrate Design, Multi-Die Integration, Chiplet Packaging, Package Design, Siemens Xpedition, Cadence Allegro APD, Semiconductor Layout, ASIC, packaging technology, Package Design, Package Design Engineer

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