Design Verification Engineer

Job Overview

Ensure functional correctness, performance, and compliance with specifications for complex digital ASIC Core/IP designs. This role emphasizes deep, unit, and core-level verification.

Key Responsibilities

• Plan: Develop comprehensive Core Verification Plans based on micro-architecture and design specifications.
• Develop: Architect and implement reusable, robust verification environments using SystemVerilog/UVM.
• Test: Create and execute constrained-random and directed tests to achieve high functional and code coverage.
• Debug: Analyze simulation results, troubleshoot complex failures, and collaborate with design teams to identify and resolve issues.
• Automate: Build and maintain scripts (Python/Perl) to improve verification flow and regression management.

Requirements

• Mandatory: Expertise in SystemVerilog/UVM.
• Experience: Minimum 7 years of hands-on verification experience.
• Strong understanding of digital logic design and verification methodologies.
• Proven experience verifying digital systems with standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
• Ability to work independently and provide constructive feedback to RTL design teams and CPU/IP micro-architects.
• Proficiency with industry-standard EDA simulation and debug tools.
• Solid debugging and root-cause analysis skills.
• Scripting experience (Python, Perl).
• Excellent written and verbal communication skills in English.
• The anticipated salary range is anywhere from $100,000 to $150,000.

Exact compensation may vary based on several factors, including skills, experience, and education. Benefit packages for this role will start on the 1st day of employment and include medical, dental, and vision insurance, as well as HSA, FSA, and DCFSA account options, and 401k retirement account access with employer matching. Employees in this role are also entitled to paid sick leave and/or other paid time off as provided by applicable law.