Title: Physical Design STA Engineer

Location: San Jose, CA 95134

Duration: 6 Months

Job Description:

• Sr. STA Engineer with 15 years experience for STA position (Physical Design Static Timing Analysis / STA Engineer).
• Perform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for SoCs.
• Strong understanding of digital design concepts, including synthesis, timing analysis, and formal verification.
• Expert in Synopsys timing analysis tool Primetime.
• Experience in timing ecos using Synopsys and other tools.
• Familiarity with scripting languages like TCL, Perl, or Python for automation tasks.
• Knowledge of ASIC design flow, including front-end and back-end processes.

Requirements:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• Ability to collaborate effectively in a team environment and communicate complex technical concepts clearly.
• Strong problem-solving skills and attention to detail.
• Understanding of semiconductor fabrication processes and how they influence IC design.
• Experience with low-power design techniques is a plus.
• Knowledge of analog and mixed-signal design principles is beneficial for certain roles.
• Willingness to stay updated on the latest advancements in semiconductor technology and design methodologies.