Title: Pll Circuit Design Engineer - Hybrid

Description:

THE PERSON:
Solid knowledge Analog Circuit Design in FinFET technology specifically in PLLs and associated subblocks including VCO, charge-pump, dividers, state machines, LDO, feedback and compensation techniques, bandgap, TDC, interpolator circuits, high speed buffers etc.
Solid knowledge of industry standard tools and practices for analog circuit design
Good knowledge in Physical design, STA, methodology scripts (Tcl), knowledge on Perl, Python
Quality-oriented mindset
Strong and effective communication skills and team spirit

KEY RESPONSIBILITIES:
Help design of building blocks of a PLL
Run pre-tapeout verification flows to confirm design meets performance, power, reliability and timing requirements.
Work closely with layout engineers to deliver the physical design as well as define production/bench-level test plans with post-silicon characterization groups for silicon evaluation to ensure interlocked and high-quality execution

PREFERRED EXPERIENCE:
3-5 years of professional experience in the semiconductor industry
Experience in FinFET & Dual Patterning nodes such as 16/14/10/7nm/5nm
Hands-on design experience in performance analog and hybrid Phase Locked Loops, analog-to-digital (ADC), digital-to-analog (DAC) data converter, VCO, LDO, bandgap, charge pump, op-amps, interpolator circuits.
Experience with the following is a plus: Digital PLL techniques, TDC or DSP and control theory experience related to digital PLLs, Dual charge-pump PLL designs, Fractional-N PLLs, spread-spectrum PLLs.
Proficient with Cadence custom circuit design tools like ADE-L and ADE-XL and running Monte-Carlo, noise, aging, EM and IR drop simulations and stability analysis. Helic/EMX is a plus.
Have good experience with simulation tools such as Spectre, Hspice, AFS, and MATLAB, System Verilog, Python.
Capable of understanding DRC and LVS results with verification tools (Calibre, ICV, or like)
Proficiency in scripting languages like Perl, Python, matlab etc. is a plus.
Able to work effectively in a team, with good interpersonal skills, enthusiasm and positive energy
Possess strong analytical/problem solving skills and pronounced attention to details
Must be a self-starter, and able to independently drive tasks to completion

ACADEMIC CREDENTIALS:
Master s in electrical engineering or equivalent preferred

Hybrid. 2-3 days onsite.

Mandatory skills:

FinFET, Dual Patterning nodes Required Skills (OR) OR
Digital PLL techniques, TDC, DSP, Dual charge-pump PLL designs, Fractional-N PLLs, spread-spectrum PLLs,
analog-to-digital, ADC, digital-to-analog, DAC, data converter, VCO, LDO,
circuit design tools, ADE-L, ADE-XL, EM, IR drop simulations, Helic, EMX,
Spectre, Hspice, AFS, and MATLAB, System Verilog, Python, DRC, LVS, verification tools, Calibre, ICV,
scripting languages, Perl, Analog Circuit Design, VCO, charge-pump, TDC, interpolator circuits

VIVA USA is an equal opportunity employer and is committed to maintaining a professional working environment that is free from discrimination and unlawful harassment. The Management, contractors, and staff of VIVA USA shall respect others without regard to race, sex, religion, age, color, creed, national or ethnic origin, physical, mental or sensory disability, marital status, sexual orientation, or status as a Vietnam-era, recently separated veteran, Active war time or campaign badge veteran, Armed forces service medal veteran, or disabled veteran. Please contact us at for any complaints, comments and suggestions.

Contact Details :

Account co-ordinator: Godwin D Antony Raj

VIVA USA INC.
3601 Algonquin Road, Suite 425
Rolling Meadows, IL 60008
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