Experienced engineer focused on Security Subsystem Microarchitecture and RTL. The person coming into this role will work on the implementation of security solutions for server-class CPU and AI/ML accelerator chiplets.

This role is hybrid, based out of Austin, TX, Santa Clara, CA, Boston, MA or Toronto, Ontario.

Responsibilities:

• RTL design and Microarchitecture of a security sub-systems including features responsible for life-cycle management, Root-of-Trust, and cryptographic algorithms and accelerators
• RTL coding in Verilog leveraging both industry tools as well as open-source infrastructure
• Work with design, test and post silicon validation teams for high quality delivery of the security subsystem
• Evaluate and integrate 3rd party IP components in the design
• Drive trade-offs for your logic by working closely with architecture, DV and physical design engineers to craft optimal solutions that meet the design goals
• Deploy innovative techniques for improving power, performance and area of the design, drive experiments with RTL and evaluate synthesis, timing and power results
• Debug RTL/logic issues across various hierarchies (core, chip) in both pre-silicon and post-silicon environment
• Enhance RTL design environment, tools and infrastructure

Experience & Qualifications:

• BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of experience
• Strong background and experience with cryptographic algorithms, Root-of-Trust, key management and other security infrastructure
• Knowledge of security assurance testing
• Knowledge of industry standard protocols such as AXI, AHB, APB
• Expertise in logic design and ability to evaluate functional, performance, timing and power for you design
• Strong experience with hardware description languages (Verilog, VHDL), simulators (VCS, NC, Verilator), Synthesis and Power tools
• Expertise in microarchitecture definition and specification development
• Strong problem solving and debug skills across various levels of design hierarchies