You haven't searched anything yet.
The role is Design for Test (DFT) for high-performance designs going into industry leading AI/ML architectures. The person coming into this role will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage, and facilitating debug and yield learnings while minimizing design intrusions. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC.
This role is hybrid, based out of Santa Clara, CA or Austin, TX
Responsibilities:
Experience & Qualifications:
Full Time
Durable Manufacturing
$136k-156k (estimate)
03/10/2024
07/11/2024
tenstorrent.com
TORONTO, ONTARIO
50 - 100
2016
LJUBISA BAJIC
<$5M
Durable Manufacturing