Rivos is on a mission to build the best RISC-V enterprise systems in the world with class leading performance, power, security and RAS features. We are seeking Die-to-Die Interconnect/Fabric Design experts to join our team in building the best RISC-V compute systems in the world.

Responsibilities

• Microarchitecture development and specification - from early high-level architectural exploration through micro architectural research and arriving at a detailed specification
• Development, assessment, and refinement of RTL design to target power, performance, area, and timing goals
• Validation - support test bench development and simulation for functional and performance verification
• Performance exploration and correlation - explore high performance strategies and validate that the RTL design meets targeted performance
• Design delivery - work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and power

• Thorough knowledge of large scale Die-to-Die coherent or non-coherent interconnects
• Knowledge of one or more network protocols: UCIe, PCIe, AMBA, AXI, CHI, ACE, Tilelink or similar protocols
• Prior work experience in design of digital portion of high speed, high bandwidth IO interfaces
• Knowledge of cache coherent memory systems and interconnect, including cache coherence protocols like MESI, MESIF, MOESI or other similar protocols
• Familiarity with different network topologies (ring, mesh, xbar etc)
• Proficiency in SystemVerilog or Verilog RTL coding
• Experience with simulators and waveform debugging tools
• Understanding of microarchitecture and logic design trade-offs for high performance, lower power, area and timing

• PhD, Master’s Degree or Bachelor’s Degree in technical subject area.