Architecture study and evaluation of advanced SerDes topologies such as 112Gbps PAM-4 and beyond SerDes design and verification of different high speed analog and mixed signal blocks including, but not limited to: drivers, front end circuits, samplers, comparators, ADCs, DACs, PLLs, clock distribution, etc. Evaluate, measure, and debug silicon until it reaches high volume production. Work with cross functional teams to optimize the designs.

* MS or Ph.D with a major in EE or Physics related field. Solid background in analog CMOS circuit design. Proficient with Cadence design environment and mixed-signal simulation. Able to assume responsibility for a variety of technical tasks and to work independently. (recommended) Digital communication system, digital signal processing, digital system design, RF system, MATLAB.