About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

What You Can Expect

You will spearhead the in-depth circuit analysis for intricate sub-circuit blocks within our overall design, meticulously accounting for Process, Voltage, and Temperature (PVT) considerations. Your expertise will be pivotal as you mentor and guide team members, leveraging your profound knowledge to optimize performance within stringent area and power constraints. Comfortable mentoring up to 3 team members, your daily activities encompass iterative testing, comprehensive documentation, and summarization of findings, fostering collaboration with the global team through regular meetings to ensure coherence within the extended 6-12 month project cycles. Proficiency with tools such as Cadence Xcelium/Virtuoso/Innovus, Design Compiler, Python, Perl, and the Microsoft Office Suite will be crucial, and your adeptness in a Linux environment will contribute to the seamless execution of your responsibilities.

What We're Looking For

To be successful in this role, you must:
- Have a Bachelor's or Master's in Electrical Engineering, Computer Engineering, Computer Science, or similar field. Degrees in mathematics, physics or other sciences may be considered provided adequate coursework in electronics was taken also or work experience has provided relevant knowledge since graduation.
- Independently analyzes and optimizes multiple sub-circuit blocks within our overall design across Process, Voltage, Temperature.
* Defines circuit specifications and optimizes for team members to follow and implement.
* Identifies unexpected interactions across multiple sub-circuit blocks and proposes circuit updates to address marginality issues.
* Responsible engineer for at least one PMIC design including architecture definition, design specifications, milestone and resource planning for the team.
* Identifies and proposes innovative solutions to enhance the overall design.
* Leads root cause investigation and silicon validation of model to hardware correlation issues.

* Previous experience with mixed-signal design environment and power management ICs (Buck, Boost, DC/DC architecture).

* Attends and participates in customer requests and feedback.
* Circuit design expert in digital domain.
* Attends and participates in customer requests and feedback.

* Highly skilled at RTL design and implementation using Verilog or systemVerilog.

* Front-end synthesis and static timing expertise.

* DFT/ATPG architecture and implementation experience.

* Previous experience overseeing back-end PD implementation.

* Solid understanding of UVM testbench and stimulus concepts.

#LI-TD1

Expected Base Pay Range (USD)

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.