Staff Engineer, Layout Design: In this job, you will be working with a world-class team of engineers to develop novel SoC products for connectivity and communications. You will be responsible for IC layout of analog/mixed-signal, RF, and digital designs in CMOS technologies. Our ideal candidate is methodical, diligence, and discipline.

This is a contract position in San Jose, CA.

Key Responsibilities

• Hierarchical floor planning, supply/interconnect planning, die size estimation
• Layout of block and top-level cells in deep sub-micron CMOS technologies
• Improving the flows related to the development and debug of large SOC layouts
• Work closely with design engineers and digital counterparts developing a solid, efficient, and robust device physical design

Job Requirements

• AA/AS Degree in Layout Design or related field or equivalent experience
• Ten or more years commercial experience of developing physical designs
• Highly skilled in navigating through, summarizing and improving Calibre DRC, ERC, LVS, etc. results
• Solid knowledge of Cadence layout and Mentor Graphics Calibre tools
• Analytical and disciplined problem solver
• Team player with a strong sense of urgency to meet product needs on time
• Good verbal and written communication and presentation skills

Desirable Skills

• Use of scripting to automate and/or improve layout flows is desired but not required
• Experience working on or leading a chip top physical design