2 Verification Engineer Jobs in Fremont, CA
Happiest Minds Technologies Limited is Hiring a Verification Engineer Near Fremont, CA
Job Details
Verification Engineer
Fremont, CA
BSEE or BSCS, or equivalent
- 5 years of ASIC/FPGA verification experience using SystemVerilog / UVM
- Must have experience with:
- Verification flow using Questa simulation
- Developing verification plans
- Designing and implementing SystemVerilog / UVM test benches for constrained-random verification
- Developing functional coverage models
- Writing and debugging directed and random test cases
- Experience with automation/scripting (Python, Perl, sed, awk, tcl/tk, sh)
- Experience with the following is a plus
- C programming desirable. SystemC and C used in conjunction with chip design and verification
- Experience with Formal verification / property-checking
- Experience with emulation or FPGA prototyping
- Knowledge of standard protocols (such as PCIe)
- Knowledge of DO-254
- FPGA experience
- Good communication skills
Job Description:
- Deliver consulting services covering functional verification flow implementation.
- Work with customer to implement and deploy advanced verification methodologies.
Job Summary
Full Time
$70k-94k (estimate)
05/01/2024
06/30/2024
happiestminds.com
Bengaluru, MN
200 - 500
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