Position: Senior Formal Verification Engineer
Location: 100% remote (work from any US location)
Status: US Citizen or US Permanent Resident only
Full-time: Salary Benefits Bonuses or Contractor
About the project:
As a senior member of an SOC development team, you would be responsible for driving the Design Verification of either blocks (units) or full-chip elements of innovative SOC designs. You will leverage your Formal Verification experience to develop verification plans, create environments and use formal tools to prove the correctness of the design. If you have SOC integration verification experience, joining the Encore Semi Verification team could be for you.
Minimum Qualifications:
• Knowledge of SoC/CPU/GPU designs, VLSI, and digital logic design and verification techniques
• Experience with formal property proofs on industrial strength designs and architectures
• Deep understanding of SoC design and verification
• Good understanding of formal verification technologies/abstraction techniques
• Temporal logic assertion-based languages such as SVA or PSL
• Experience in using EDA formal tools
• Proficiency in scripting languages and excellent debugging skills 
• Experience with Cadence Formal Verification tools such as JasperGold
• System Verilog and UVM methodology expertise
• Must have 5 years of experience and BSEE, MSEE preferred
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