Do you thrive on designing high-performance circuits and pushing the boundaries of technology? We're searching for a talented Analog PLL Design Engineer to join a growing team. You'll play a critical role in creating innovative, production-ready designs that power the next generation of cutting-edge products.
Responsibilities:
Design robust analog PLLs using leading-edge FinFet technologies.
Master the challenges and opportunities of physical layout.
Collaborate with colleagues to expand your expertise in diverse areas.
Contribute to design methodologies that set industry standards.
Analyze and present complex data with clarity and impact.
Required Skills:
10 years of experience in BSEE, MSEE, or PhD level EE.
Proven track record designing PLLs in CMOS technologies
Deep understanding of physical layout constraints and their impact
Experience taking circuits/SOCs to production.
Proficiency with version control systems (git is a plus)
Nice to have:
High-speed datacomm design experience
Advanced software programming skills (OOP, Python, C )
Familiarity with Python libraries.
Experience with Git and silicon bring-up/testing.
The anticipated annual base salary for this position is between $145,000 - $220,000 which also includes a comprehensive benefits package.