We are looking for Senior FPGA/RTL Design Engineer - Remote / Telecommute for our client in Hillsboro, OR
Job Title: Senior FPGA/RTL Design Engineer - Remote / Telecommute
Job Location: Hillsboro, OR
Job Type: Contract
Job Description:
Pay Range: $60hr - $65hr

• The hire will be involved in deep sub-micron IC logic and VLSI design, validation, development, developing, verifying, and validating competitive solutions with Client's PROM circuit technology for use in mobile, IOT, client, network, and server segments.
• Include RTL design and validation for Fuse Soft IP, developing tests for designs and validating PROM Sub-system, IP, and Controller designs, identifying potential design limitations and bugs that can impact design margin and component yield.
• Provides Post-Si support, including but not limited to characterization, test definition, debugging product returns as well as reviewing and dispositioning results.
• Clear documentation and communication skills: thorough, concise, effective documentation of logic design, verification and testing is expected, as well as IP integration support to SoC customers, timely communication, and careful consideration of customer requests.

Minimum Qualifications:

• Bachelor s degree in electrical engineering with 3 experience or master s degree in electrical engineering or related field with 2 year experience.
• Experience in Logic design, validation, and testing, including but not limited to.
• Micro-architecture definition of design features, test plan creation and functional verification.
• Effective behavioral modeling and testing of circuits in Verilog and System Verilog, as well as logical equivalence verification between Schematic and Verilog models.
• UPF (Unified Power Format) creation using low power techniques and handling multiple power domain design.
• Knowledge of Clock Domain Crossing, Design for Test, Register Description Language.
• Experience in test bench creation to generate test patterns and vectors.
• Experience with FEV (Formal Equivalence Verification) and GLS (Gate Level Simulations).

Preferred qualifications:

• Solid understanding of state machines and industry-standard protocols such as JTAG.
• Knowledge of UVM and OVM verification.
• Experience in Pre-Si validation - creation of test plan, test bench & test case development, review and debug of test results, and coding assertions to prevent illegal states.
• Experience in product development and testing using industry-standard tools.
• Experience in scripting languages (perl, tcl, etc.) to enhance automation in design, validation and testing is recommended.