Cornelis Networks is a well-funded, fast-growing start-up technology leader delivering purpose-built, high-performance fabrics accelerating High Performance Computing, High Performance Data Analytics, and Artificial Intelligence workloads in the Cloud and in the Data Center.

Our cutting-edge products empower a diverse clientele comprising scientific, academic, governmental, and commercial entities to conquer some of the world's most complex problems. By strategically harnessing the computational might of numerous processing devices at scale, we facilitate an efficient focus on a singular problem. This simultaneous optimization significantly enhances result accuracy and reduces time-to-solution for their most intricate application workloads.

Operating on a global scale, Cornelis Networks provides comprehensive end-to-end interconnect solutions. This is made possible through a well-established network of server Original Equipment Manufacturers (OEM) and channel partners. With unwavering commitment, we are dedicated to driving innovation and facilitating breakthroughs that redefine the boundaries of what is achievable in the realm of high-performance computing.

We are hiring talented ASIC Design Engineers with deep experience in one or more of the key areas required to build the world-class SoCs to be deployed in high performance computing, high performance data analytics, and artificial intelligence interconnect solutions.

Key Responsibilities

• End-to-end SoC/ASIC development:
• Front-end standard cell ASIC development including RTL development, Design Verification, synthesis, and post-silicon validation.
• Cross-functional collaboration and partnering with internal and external cross-functional teams, across all levels of the corporation.
• Define, implement, debug, and deliver system solutions around purpose-built ASICs.

Minimum Qualifications

• 3 years' post-college experience with silicon development 
• 3 years' post-college experience in digital design with one or more HDL language (System Verilog, Verilog, VHDL)
• 3 years' post-college experience in one or more scripting language (TCL, Python, Perl)
• Understanding of Standard Cell ASIC development flow including digital design, IP integration, simulation and synthesis.
• B.S. or M.S. degree in Computer Engineering, Computer Science, or Electrical Engineering

Preferred Qualifications

• Track record of first-pass success in ASIC and Systems
• Experience with multiple clock designs and asynchronous interfaces

Location

For this position, Cornelis Networks fully supports remote employees who live within the United States and are able to travel to our corporate offices in Chesterbrook, PA periodically for in-person collaboration. 

Immigration Information

To qualify for this position, candidates must be located in the United States, legally authorized to work in the U.S. and must not need U.S. Visa sponsorship now or in the future.

Cornelis Networks is an equal opportunity employer, and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity or expression, pregnancy, age, national origin, disability status, genetic information, protected veteran status, or any other characteristic protected by law.

Cornelis Networks does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services.

Job Code: AS-28B