Senior Digital Verification Engineer

Our client is a global leader in high-speed networking and communications technologies, developing advanced semiconductor and connectivity solutions that power next-generation data infrastructure. Their products sit at the forefront of networking, optical communications, and high-performance computing, enabling faster, more reliable data transmission across some of the world's most demanding environments. With a strong engineering culture and a focus on innovation, they are building the technologies that underpin the future of global connectivity.

They are seeking a Senior Digital Verification Engineer to play a key role in the verification and validation of advanced digital communication and signal processing systems. This position will focus on developing robust verification strategies for complex digital subsystems used within high-performance networking and connectivity products. You will work closely with architects, design engineers, and systems teams to ensure comprehensive functional coverage and product quality across sophisticated hardware designs.

Key Responsibilities:

• Analyze architecture and functional specifications to define verification requirements and verification strategies.
• Develop comprehensive verification plans, functional coverage plans, and formal verification approaches.
• Design and implement verification environments using SystemVerilog, UVM, and assertion-based verification methodologies.
• Develop verification components including agents, scoreboards, monitors, and reusable testbench infrastructure.
• Create directed and constrained-random test scenarios to validate complex digital designs.
• Execute coverage-driven verification methodologies and track verification progress against coverage goals.
• Monitor regressions, analyze failures, and collaborate with design engineers to debug and resolve issues.
• Support both simulation-based and formal verification flows.
• Participate in technical reviews and contribute to continuous improvement of verification methodologies and best practices.
• Work closely with architects, designers, and fellow verification engineers throughout the development lifecycle.

Key Qualifications:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• Strong expertise in SystemVerilog and SystemVerilog Assertions (SVA).
• Deep understanding of digital verification methodologies and simulation-based verification flows.
• Experience defining verification plans, coverage models, and validation strategies for complex digital designs.
• Strong analytical, debugging, and problem-solving skills.
• Excellent written and verbal communication skills.
• Ability to work independently while collaborating effectively within cross-functional teams.

Preferred Experience:

• Hands-on experience with UVM-based verification environments.
• Experience with formal verification methodologies and tools.
• Background verifying DSP, signal processing, or forward error correction (FEC) designs.
• Exposure to mixed-signal validation environments.
• Familiarity with networking and communications protocols, including optical transport technologies, high-speed Ethernet, or broadband communications standards.
• Experience using Git or similar version control systems.
• Familiarity with bug tracking and engineering workflow tools.
• Programming or scripting experience in Python, C/C , Bash, SystemC, or Make.

What Makes a Strong Candidate:

• Proven experience owning verification efforts for complex digital subsystems.
• Ability to develop scalable, reusable verification environments and methodologies.
• Strong debugging instincts and attention to detail.
• Comfortable collaborating across architecture, design, and verification teams.
• Passion for delivering high-quality silicon and solving challenging technical problems.

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