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Senior Digital Verification Engineer - UVM / System Verilog

USA Tech Recruit
Rochester, NY Full Time
POSTED ON 6/2/2026
AVAILABLE BEFORE 7/1/2026

Senior Digital Verification Engineer - UVM / System Verilog


We are partnered with a global leader in high-speed optical networking and telecommunications connectivity solutions. The team is looking to hire a Senior Digital Verification Engineer to simulate and validate high-performance subsystems for their flagship optical products.


This is a permanent working opportunity based in Rochester, New York.


Key responsibilities for this Senior Digital Verification Engineer position:

  • Collaborate with systems engineers to define and implement verification strategies for complex functional blocks.
  • Build robust testbench environments, components, agents, and scoreboards using SystemVerilog UVM or C.
  • Author comprehensive verification, functional coverage, and formal verification test plans.
  • Run coverage-driven verification, monitor regressions, and debug failures alongside the digital design team.
  • Take complete accountability for the functional validation of major architectural blocks using simulation and formal methods.


Key requirements:

  • Advanced expertise with SystemVerilog, SystemVerilog Assertions (SVA), and major EDA simulation tools.
  • Experience with UVM and formal verification methods (highly preferred).
  • Background in Digital Signal Processing (DSP), Forward Error Correction (FEC), or protocols like OTN and Ethernet.
  • Proficiency in scripting and programming languages (Python, C/C , Make, Git).
  • Degree in Electrical Engineering, Computer Science, or a related scientific discipline.
  • Highly motivated self-starter with a methodical approach to complex problem-solving.


Keywords: Senior Digital Verification Engineer / SystemVerilog / UVM / SVA / ASIC / SoC / DSP / FEC / Optical Networking / OTN / Ethernet / Simulation / Rochester / New York / Semiconductor


If you are interested in this Senior Digital Verification Engineer position, please send a CV to ts@eu-recruit.com


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Salary.com Estimation for Senior Digital Verification Engineer - UVM / System Verilog in Rochester, NY
$127,798 to $143,551
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