What are the responsibilities and job description for the Senior Validation Engineer position at TPI Global Solutions?
• 𝙊𝙣𝙡𝙮 𝙒2 – 𝙉𝙤 𝘾2𝘾 / 1099
We are looking for a highly skilled Senior Validation Engineer to support platform-level electrical and functional validation for next-generation processor and memory subsystems. This role requires strong hands-on experience in memory interface bring-up, FPGA-based validation, and lab-level debugging of high-speed interfaces.
This is a 100% onsite role in Santa Clara, CA.
The project is long-term with strong potential for extension.
Key Responsibilities
- Develop and execute functional and electrical validation test plans for DDR4/DDR5, LPDDR4/LPDDR5 memory interfaces.
- Perform platform bring-up, silicon debug, and root-cause analysis across memory controller/PHY, NOC, and related high-speed interfaces.
- Use oscilloscopes and other lab equipment to validate and characterize memory subsystems.
- Work with FPGA platforms, embedded processors, and associated toolchains for validation.
- Collaborate with cross-functional hardware, firmware, and system engineering teams.
- Provide detailed input on platform design and support validation activities across the full lifecycle.
Required Skills & Experience
- 7–10 years of hands-on experience in memory interface bring-up or validation (DDR4/DDR5, LPDDR4/5).
- Strong lab experience using oscilloscopes, logic analyzers, signal measurement tools.
- Scripting experience: Python and/or Tcl.
- 3–4 years of experience with FPGA bring-up or FPGA-based validation.
- Working knowledge of embedded processors, and tools such as Vivado and Vitis.
- Strong understanding of platform-level electrical and functional validation methodologies.
- Excellent communication and cross-team collaboration skills.
Preferred Qualifications
- Bachelor’s in Electrical/Computer Engineering (Master’s preferred).
- Experience with high-speed interfaces, signal/power integrity, or system-level silicon validation.