Principal ASIC Physical Design Engineer (1151828)

Location: SAINT PAUL, MN, USA

Salary: $195,000.00 USD Annually - $220,000.00 USD Annually

Description

Title: ASIC Physical Design / Static Timing Analysis (PD/STA) Engineer

Type: Full Time

Location: Remote - CST Hours

Seeking a highly experienced ASIC Physical Design / Static Timing Analysis (PD/STA) Engineer to join our team onsite in St. Paul, Minnesota. This role supports ASIC, IP, and chiplet development programs and is best suited for senior-level engineers with extensive experience driving RTL-to-GDSII physical design implementation and signoff through tape-out.

Responsibilities

• Lead and collaborate with analog, verification, logic design, and physical design teams throughout the implementation cycle, from synthesis through tape-out, for IP, test chip, SoC, and ASIC designs.
• Drive block-level and chip-level physical design implementation using industry-standard place-and-route (PnR), static timing analysis (STA), and EMIR tools and methodologies.
• Own end-to-end timing closure activities, including multi-corner multi-mode (MCMM) analysis, optimization, and ECO implementation.
• Partner with cross-functional teams to resolve technical challenges and implement improvements to tools, flows, and design methodologies.
• Mentor engineering team members through technical reviews, best-practice guidance, and hands-on project support.
• Improve engineering productivity through automation, infrastructure development, and methodology enhancements.
• Support project planning efforts by identifying risks, tracking progress, and communicating status updates to technical and program leadership.
  
  

Required Qualifications

• Bachelor’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field with 15 years of relevant experience; or Master’s degree with 12 years of relevant experience; or PhD with 8 years of relevant experience.
• Experience working with advanced semiconductor process nodes and a strong understanding of deep submicron design challenges and closure methodologies.
• Extensive knowledge of SoC and ASIC physical design flows, tools, and implementation methodologies.
• Experience with low-power design techniques, including power gating, multi-Vt optimization, and voltage scaling.
• Strong understanding of digital logic design fundamentals and gate-level and transistor-level implementation concepts.
• Proficiency in scripting and programming languages such as Tcl, Perl, Shell, and Python.
• Strong communication and collaboration skills, with the ability to influence and work effectively across cross-functional teams.
  
  

Preferred Qualifications

• Experience supporting successful tape-outs on advanced process technologies.
• Demonstrated leadership in physical design methodology development and continuous process improvement.
• Experience mentoring and developing engineering talent in a fast-paced semiconductor environment.
  
  

Benefits

• Work-Life Balance: Flexible 9/80 work schedule with every other Friday off
• Competitive Comp & Benefits: Healthcare and medical coverage options, 401(k) retirement benefits with company contribution, generous holidays and PTO
• Incentives: Eligibility for short-term and long-term incentive programs
  
  

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Contact: amassad@judge.com

This job and many more are available through The Judge Group. Find us on the web at www.judge.com