What are the responsibilities and job description for the System IP Design Verification Engineer position at Protingent?
Job Description
Job Title: System IP Design Verification Engineer
Position Description: Protingent Staffing has an exciting contract System IP Design Verification Engineer opportunity for our client located in San Jose, CA.
Job Description:
About Protingent: Protingent is an Award-Winning provider of top-tier Engineering and IT talent, trusted by companies at the forefront of innovation — from Software and Aerospace to AI, Clean Tech, Medical Devices, and Connected Technologies. We’re passionate about making a positive impact by connecting exceptional talent with meaningful opportunities and helping our clients build the future.
Job Title: System IP Design Verification Engineer
Position Description: Protingent Staffing has an exciting contract System IP Design Verification Engineer opportunity for our client located in San Jose, CA.
Job Description:
- As a Senior Staff System IP Design Verification Contractor, you will contribute to the functional verification of System IP, including coherent interconnect and caches.
- This is a technical individual contributor role with heavily involved hands-on project execution.
- A strong background in Design Verification and hands-on experience with both block-level and top-level design is required to be successful in this role.
- Architecting and building re-usable testbenches right from scratch
- Proposing and driving best practices/methodologies/automation that can improve productivity
- Owning key features and timely execution of tasks as per milestones
- Experience with GLS [gate level simulation]
- Creating test plans as per the spec and presenting to various stakeholders
- Working with designers to resolve any spec issues
- Creating test benches, verification environments, stimulus, tests
- Collaborating with designers to verify the correctness of a design feature and resolve failures
- Developing assertions, checkers, covergroups, and SystemVerilog constraints
- Debugging and root-cause causing of functional failures from regressions
- Analyzing code and functional coverage results, performing gap analysis
- Working with the SoC team to debug functional failures during IP bringup and feature execution
- Collaborating with Physical design teams, running and debugging gate-level simulations
- Collaborating with Performance verification teams to help with co-sim TB bringup
- Bring up power-aware verification with UPF
- Helping with Silicon bringup and root-cause analysis.
- Phd/MS/BS in Electrical or Computer Engineering
- 12 years of industry experience in a design verification role
- Expert hands-on coding skills in Testbench, Stimulus, checker development, and coverage closure.
- Experience with System Verilog, UVM, or equivalent
- Knowledge of ARM protocols or equivalent protocols – CHI, AXI, ACElite, APB
- Experience with Git version control, Unix/Perl/Python scripting
- Good written and verbal communication skills
- Experience with GLS, power vector generation
- Formal verification skills will be a plus
- Combined experience with coherent interconnect, caches, and LPDDR memory controllers will be a plus.
- Job Type: Contract
- Pay Rate: $90-$120 an hour
- Location: Austin, TX or San Jose, CA (Onsite).
About Protingent: Protingent is an Award-Winning provider of top-tier Engineering and IT talent, trusted by companies at the forefront of innovation — from Software and Aerospace to AI, Clean Tech, Medical Devices, and Connected Technologies. We’re passionate about making a positive impact by connecting exceptional talent with meaningful opportunities and helping our clients build the future.
Salary : $90 - $120
