What are the responsibilities and job description for the System IP Design Verification Engineer position at Prodapt?
Overview
Prodapt is a global technology company and the largest specialized player in the Connectedness industry. As an AI-first strategic partner, Prodapt provides consulting, business transformation, and managed services to top telecom and tech enterprises. Prodapt ASIC Services is a leading provider of SoC ASIC/FPGA and Embedded Software services. We offer turnkey solutions, Offshore Design Centers (ODCs), and staff augmentation across key areas like RTL Design, UVM Verification, Emulation, FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up. Our embedded services include firmware, device drivers, RTOS porting, and board bring-up. A “Great Place To Work® Certified™” company, Prodapt employs over 6,000 technology and domain experts in 30 countries. Prodapt is part of the 130-year-old business conglomerate
The Jhaver Group, which employs over 32,000 people across 80 locations globally.
We're seeking a Verification Specialist that will be contributing directly to validation efforts on advanced system IP such as cache coherency and interconnect solutions. This is a hands-on technical lead role, centered on complex project delivery and extensive experience in both module and integration-level verification.
Looking for candidates in San Jose, CA
6 month contract
W2
Responsibilities
Prodapt is a global technology company and the largest specialized player in the Connectedness industry. As an AI-first strategic partner, Prodapt provides consulting, business transformation, and managed services to top telecom and tech enterprises. Prodapt ASIC Services is a leading provider of SoC ASIC/FPGA and Embedded Software services. We offer turnkey solutions, Offshore Design Centers (ODCs), and staff augmentation across key areas like RTL Design, UVM Verification, Emulation, FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up. Our embedded services include firmware, device drivers, RTOS porting, and board bring-up. A “Great Place To Work® Certified™” company, Prodapt employs over 6,000 technology and domain experts in 30 countries. Prodapt is part of the 130-year-old business conglomerate
The Jhaver Group, which employs over 32,000 people across 80 locations globally.
We're seeking a Verification Specialist that will be contributing directly to validation efforts on advanced system IP such as cache coherency and interconnect solutions. This is a hands-on technical lead role, centered on complex project delivery and extensive experience in both module and integration-level verification.
Looking for candidates in San Jose, CA
6 month contract
W2
Responsibilities
- Develop new, modular testbenches with reusability at the core
- Identify and champion process enhancements and automation to boost team throughput
- Drive feature ownership—manage workload to meet project targets
- Execute and interpret gate-level simulation (GLS) results
- Draft coverage-driven test plans and deliver presentations for key partners
- Partner with RTL and SoC designers to clarify requirements and resolve ambiguities
- Build and maintain verification infrastructure, tests, and stimuli
- Complete design feature validation hand-in-hand with architects; troubleshoot failures
- Design assertions, checkers, coverage strategies, and random constraints in SystemVerilog
- Investigate and debug test failures, tracing to root causes across regressions
- Assess and report coverage data, identifying gaps for closure
- Support full-chip bring-up alongside SoC and performance engineering teams
- Analyze and solve issues found in gate-level and power-aware scenarios (UPF)
- Contribute to post-silicon debug activities as needed
- Familiarity with ARM-based standards, for example CHI, AXI, ACE-Lite, APB, etc.
- Expertise in source control systems (Git) and typical scripting languages (Unix, Perl, Python)
- Skilled communicator with proficiency in technical documentation and discussions
- Track record of working with GLS and power simulation flows
- Exposure to formal property checking is a plus
- Direct experience spanning cache/interconnect validation and LPDDR memory is especially valued
