What are the responsibilities and job description for the Design Verification Engineer - Internal IP position at Etched?
About Etched
Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents.
Job Summary
We are seeking a Design Verification Engineer to join our Internal IP DV team. You will ensure the custom IPs powering Sohu — including systolic arrays, DMA engines, and NoCs — are robust, high-performance, and silicon-ready. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges. You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack.
Key Responsibilities
Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents.
Job Summary
We are seeking a Design Verification Engineer to join our Internal IP DV team. You will ensure the custom IPs powering Sohu — including systolic arrays, DMA engines, and NoCs — are robust, high-performance, and silicon-ready. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges. You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack.
Key Responsibilities
- Develop and maintain UVM/SystemVerilog testbenches for high-performance IPs (compute arrays, DMAs, NoCs, memory subsystems).
- Define and execute verification plans covering functional correctness, corner cases, concurrency, and performance bottlenecks.
- Debug complex datapath and protocol issues in RTL and testbench environments.
- Work closely with architects and designers to validate functionality and design intent.
- Partner with SW, FW, and emulation teams to ensure end-to-end bring-up and debug coverage.
- Contribute to reusable DV infrastructure, coverage models, and methodology improvements.
- Proficiency with UVM and SystemVerilog.
- Strong debugging and problem-solving skills for complex digital designs.
- Solid knowledge of computer architecture and digital design fundamentals.
- Hands-on experience verifying datapaths, memory systems, interconnects, or high-throughput fabrics.
- Familiarity with SystemVerilog Assertions (SVA) and formal verification techniques.
- Experience verifying systolic arrays, DMA engines, or NoC/AXI protocols.
- Scripting skills (Python/Perl/TCL or similar) for automation, debug and regression flows.
- Full medical, dental, and vision packages, with generous premium coverage
- Housing subsidy of $2,000/month for those living within walking distance of the office
- Daily lunch and dinner in our office
- Relocation support for those moving to San Jose (Santana Row)
Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
Salary : $2,000
