Staff ASIC Design Engineer

We are seeking a Senior SoC Design & Integration Engineer to lead the architecture, design, and implementation of complex SoCs for next-generation compute platforms.

This role focuses on high-speed interconnects, IP integration, and ASIC/SoC execution, with emphasis on UCIe, HBM subsystems, NoC fabrics, and custom compute cores.

The role includes RTL development, IP configuration and integration, synthesis, and collaboration with physical design teams for timing closure and implementation.

The engineer will help ensure efficient interaction between high-performance UCIe interfaces, NoC fabrics, memory systems, and processing elements in advanced SoC and base-die architectures.

Key Responsibilities

• Define SoC and subsystem architecture for UCIe, NoC/fabrics, memory controllers, PHYs, and compute cores.
• Integrate high-speed IPs (UCIe/HBM) and configure NoC interconnects.
• Develop microarchitecture, RTL design, and perform RTL quality checks.
• Run synthesis, lint, CDC/RDC checks, and timing/power closure activities.
• Optimize designs for power, performance, and area (PPA) and support system-level performance simulations.
• Collaborate with physical design teams on floorplanning, CTS, routing, and power integrity.
• Work closely with architecture, firmware, RTL, and validation teams to ensure system functionality.
• Support verification planning, functional coverage, and SoC-level validation.
• Mentor junior engineers and improve design methodologies.

Required Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• 10 years of experience in ASIC/SoC design, integration, and implementation.

Technical Expertise

SoC Design & Integration

• Strong experience with RTL design and integration (Verilog/SystemVerilog).
• Experience integrating UCIe, HBM, memory controllers, and NoC interconnects.
• Knowledge of high-speed interface integration.