Senior FPGA Engineer

Build the FPGA core of next‑gen brain imaging

You’re not looking for another incremental FPGA role. You want to own the silicon heartbeat of a system that actually matters.

In this role, you’ll architect and deliver the FPGA subsystems that power a cutting-edge functional brain imaging platform. You’ll take designs from blank page through architecture, implementation, verification, and into the lab on real hardware.

You’ll live at the hardware/software boundary—owning high-speed links, real-time control, and DSP data paths that keep an ultra-sensitive sensor array stable and fast.

When your timing closes and your links lock, neurologists and researchers get clearer windows into the human brain.

If you’ve taken complex FPGA subsystems from concept to production and love hands-on lab work, we want to talk to you.

You’ll be at the center of a high-performance FPGA platform for a full-head brain measurement system:

• Core FPGA architecture for a production brain-imaging system
• High-speed serial transceiver links between system chassis
• DDR4-based memory subsystems on a System on Module
• Real-time DSP and control paths for sensor stability
• Arria 10 FPGA timing, resources, and test strategy
• Simulation and verification environments
• Hardware/software integration with embedded processors
• On-system testing using a deployed neuroimaging platform

You’ll work directly with technologies like SystemVerilog, high-speed SerDes, DDR4, Intel/Altera Arria 10, and SoC-style register maps and DMA.

Your challenge: keep a whole-head sensor array rock-solid and real-time, in the real world.

• Architect FPGA subsystems for the next-generation brain imaging system
• Implement and verify FPGA designs in SystemVerilog
• Design and implement high-speed serial transceiver links between chassis
• Design and integrate DDR4 memory on the System on Module
• Improve real-time control and DSP data paths including filtering, decimation, and feedback loops
• Drive timing closure, resource budgeting, and design-for-test on Arria 10 devices
• Build and maintain simulation and verification environments
• Partner closely with embedded software on register maps, DMA, and SoC integration
• Contribute to design documentation and verification evidence within an ISO 13485 design control process
• Participate in on-site testing and measurements using the full HEDscan system
• Troubleshoot complex FPGA, signal integrity, and lab issues hands-on
• Operate independently in a fast-moving, small-team environment

• B.S. in Electrical Engineering, Computer Engineering, or closely related field (M.S. preferred)
• 7 years of professional FPGA design experience with end-to-end subsystem ownership
• Strong SystemVerilog design experience
• Hands-on design and debug of high-speed serial transceivers (SerDes, multi-gigabit links, CDR, equalization, jitter/eye work)
• Practical DDR4 experience including controller integration, calibration, timing closure, and throughput debug
• Strong lab, measurement, and debug skills
• Self-directed, independent, and comfortable learning on the fly
• Ability to work on-site in Louisville, CO

You’ve shipped serious FPGA-based systems where you owned high-speed I/O, memory, and real-time DSP/control—and you can tell the war stories. You know how to squeeze margin out of timing, bring up DDR4 in the lab, and make multi-gigabit links behave.

You might have touched Intel/Altera Arria 10 or Efinix parts, worked in a regulated environment, or integrated hard processors and C firmware into a coherent SoC-style platform.

High-signal technologies and domains: Intel/Altera Arria 10 • Efinix Trion T20 • SystemVerilog • SerDes • multi-gigabit links • DDR4 controllers • digital filters • feedback loops • closed-loop sensor control • C • System-on-Chip development • Arria 10 HPS • ISO 13485 • IEC 62304 • design controls • V&V documentation • Git

This is a chance to be the go-to FPGA expert on a small, fast-moving team, not one of dozens on a massive program. Your designs will be central, visible, and non-optional.

You’ll see the full lifecycle—from architecture sketches to lab bring-up to live measurements on a working brain-imaging system—while working alongside scientists, engineers, and technologists.

The role comes with competitive compensation plus medical, dental, vision, 401(k) with company match, and paid time off, sick leave, and holidays—all in a setting where your work has direct clinical impact.

This is a full-time, on-site role in Louisville, Colorado; it is not eligible for remote or hybrid arrangements.

If you’re ready to own a high-impact FPGA platform and take it all the way into the lab and onto a real neuroimaging system, let’s talk.

Please send your resume to

Kevin McCarthy

Senior FPGA Engineer, FPGA Engineer, Lead FPGA Engineer, Digital Design Engineer, Senior Digital Design, SystemVerilog, Verilog, VHDL, Intel FPGA, Altera FPGA, Arria 10, Efinix, Trion T20, SerDes, high-speed serial, multi-gigabit transceivers, DDR4, memory controller, DSP, digital signal processing, control systems, feedback loops, decimation, real-time control, SoC, System-on-Chip, HPS, embedded systems, C , ISO 13485, IEC 62304, medical device, MEG, magnetoencephalography, brain imaging, Louisville CO

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