What are the responsibilities and job description for the Senior FPGA Engineer position at FieldLine Medical?
Senior FPGA Engineer (Full-Time)
Location: Onsite — Louisville, Colorado
Type: Full-time, on-site
Reports To: Director of Research & Development
ABOUT FIELDLINE MEDICAL
FieldLine Medical is a Colorado-based medical device company pioneering optically pumped magnetometer (OPM) technology for functional brain imaging. Our HEDscan system is redefining magnetoencephalography (MEG), making whole-head brain measurement more accessible than ever. We are a small, fast-moving team of scientists and engineers building technology with real clinical impact.
THE ROLE
We are looking for a Senior FPGA Engineer to improve upon the existing HEDscan FPGA architecture, help design the next-generation HEDscan system, design, verify, and implement new accessory cards for our platform. You will own FPGA subsystems end to end — from architecture through verification — working at the hardware/software boundary to keep our systems fast, stable, and reliable.
WHAT YOU’LL DO
- Architect, implement, and verify FPGA designs for our HEDscan system
- Design and implement high-speed serial transceiver links between HEDscan chassis
- Design and incorporate DDR4 memory on the System on Module
- Improve existing real-time control and DSP data paths (filtering, decimation, feedback loops) that keep the sensor array stable
- Drive timing closure, resource budgeting, and design-for-test across Arria 10 devices
- Build simulation and verification environments
- Partner with embedded software on the hardware/software boundary, register maps, DMA, and SoC integration
- Contribute to design documentation and verification evidence within our ISO 13485 design control process
- Participate in on-site testing and measurements using the HEDscan system
WHAT WE’RE LOOKING FOR
Required
- B.S. in Electrical Engineering, Computer Engineering, or a closely related field; M.S. preferred
- 7 years of professional FPGA design experience, with a track record of owning a subsystem end to end
- Experience with SystemVerilog
- Hands-on experience designing and debugging high-speed serial transceivers (SerDes, multi-gigabit links, clock/data recovery, equalization, jitter and eye-diagram work)
- Practical DDR4 experience: controller integration, calibration, timing closure, and real-world throughput debugging
- Strong lab and debug skills
- Self-directed and independent with a willingness to learn on the go
- Ability to work on-site in Louisville, CO
Nice to Have
- Experience with Intel/Altera FPGAs, particularly Arria 10
- Experience with Efinix FPGAs (Trion T20)
- DSP and control-systems background — digital filters, feedback loops, closed-loop sensor control
- C and System-on-Chip development, including Arria 10 HPS or similar hard-processor integration
- Experience in a regulated medical device environment (ISO 13485, IEC 62304, design controls, V&V documentation)
- Familiarity with Git-based workflows
COMPENSATION & BENEFITS
Base salary range: $130,000 – $165,000 per year
The posted range reflects the salary FLM reasonably expects to pay for this position at the time of posting. Actual placement within the range depends on job-related experience, depth of relevant technical skill, education, and equity.
In addition to base salary, full-time employees are eligible for:
- Medical, dental, and vision insurance
- 401(k) with company matching up to 6%
- Paid Time Off, Paid Sick Leave, and Company Holidays
WORK LOCATION
This is a full-time, on-site position at our Louisville, Colorado facility. The work is tied to hardware and lab instrumentation, so this role is not eligible for remote or hybrid arrangements.
Pay: $130,000.00 - $165,000.00 per year
Benefits:
- 401(k)
- 401(k) matching
- Dental insurance
- Health insurance
- Health savings account
- Paid time off
- Parental leave
- Vision insurance
Work Location: In person
Salary : $130,000 - $165,000