Design Verification Engineer

Job Title - SOC/RTL Verification Engineer

Job Location - Longmont, CO - 100% onsite. Hybrid option is not available

Job description -

Essential skills: RTL verification experience, Verilog/System Verilog, Modelsim/VCS, UVM

Required Experience:-

- 8 or more years of proven verification experience on Verilog and System Verilog for IP development and verification required

- Familiar with UVM verification methodologies and environments

- Strong debug skills

- Experience with simulation tools ModelSim/VCS and VIPs

- Experience in Verilog/SystemVerilog

- Strong analytical skills and attention to detail

- Excellent written and communication skills

- Familiarity with PCIe and serial protocols is a bonus

- AMD/Xilinx FPGA and tools experience is a bonus

Nice-to-have skills: FPGA Experience (Xilinx/AMD FPGA preferred), Vivado experience