DFT Engineers

Required Skills & Qualifications

• 5 years of hands-on experience in DFT and ATPG for SoC or ASIC designs

• Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing

• Proven expertise in ATPG pattern generation, analysis, and debug

• Experience with MBIST, including memory test architectures and diagnostics

• Knowledge of IO Test methodologies for interface and pin level validation

• Solid understanding of clock DFT and clock verification concepts

• Strong grasp of digital design and RTL fundamentals

• Experience with industry standard DFT/ATPG EDA tools

• Ability to work effectively in fast paced, high performance semiconductor programs

• Strong analytical, problem solving, and communication skills

• 
  Familiarity with the Siemens suite of DFT tool
• sDFT insertion for SCAN (with SSN) and MBIS
• TMBIST Repair Implementation and Verificatio
• nGenerating collaterals for Test Timing and Place and Rout
• eExpertise in IJTAG 1687 standard and good at understanding ICL and PDL standard Spe
• cVerification of DFT features, includin

gBoundary Sca

nJTA

GSCA

NMBIS

THigh Speed I