FPGA Engineer

Kelly, in partnership with Johnson & Johnson, is hiring a Senior FPGA Engineer

Description:

The Senior FPGA Contract Engineer will be responsible for enhancing and optimizing FPGA designs using Xilinx Vivado for Zynq UltraScale MPSoC devices. The ideal candidate must have strong expertise in digital logic design, hardware description languages (VHDL/Verilog/SystemVerilog), and experience with IP core integration, timing analysis, and simulation. Key responsibilities include upgrading and optimizing PCIe (from x4 to x8) and DDR interfaces, refactoring interface functionalities, and ensuring resource efficiency. Experience with embedded system co-design, AXI protocols, and hardware/software debugging is essential. The role involves working with provided design modules and requirements, delivering high-quality updated modules and standalone demonstration projects ready for integration.

Key Responsibilities include, but are not limited to:

• Update PCIe from x4 to x8
• Optimize performance for DDR interface
• Refactor some of the interface functionality
• Resource optimization, if opportunities are noted
• FPGA: Zynq UltraScale MPSoC, xczu19eg-ffvc1760-1-e
• Toolchain: Xilinx Vivado

Requirements

• Digital logic design: strong understanding of digital electronics fundamentals, including combinatorial logic (decoders, multiplexers) and synchronous logic (flip-flops, registers), reset strategy, and clocking scheme.
• Hardware description languages (HDLs): proficiency in VHDL or Verilog; SystemVerilog preferred.
• Xilinx Vivado Design Suite: expertise with FPGA design tools for Xilinx FPGA development, including synthesizing and implementing a design, and analyzing designs with the schematic viewer.
• Verification and simulation: ability to write test benches and use simulation tools to verify the functionality of HDL code before hardware implementation.
• IP cores, block design, and IP design flow
• Tcl build scripts
• Timing analysis: understanding of how to analyze and constrain timing in a design to meet performance goals, and evaluation of errors and warnings in the log files.

MPSoC-specific FPGA skills

• Processing System (PS) and Programmable Logic (PL) interaction: expertise in designing the data flow and communication interfaces between the ARM-based PS and the FPGA fabric (PL), including the use of standard protocols such as AXI4, AXI-Lite, and AXI-Stream.
• Embedded system design: knowledge of embedded software and hardware co-design principles, including understanding boot processes, memory mapping, etc.
• Xilinx Vitis Unified IDE: ability to use Vitis to generate boot.bin for hardware testing.
• Debugging: ability to debug both hardware and software, including using Vivado.