What are the responsibilities and job description for the Senior Design Verification Engineer position at Infobahn Softworld Inc?
Job Title: Desing Verification Engineer
Work Location: Austin, TX (or) Santa Clara, CA
Must Have Skills: UVM, SystemVerilog, IO/PHY verification
We are seeking a seasoned verification lead with expertise or significant interest in IO/PHY verification. You have had significant success driving IP verification, UVM and SystemVerilog.
KEY RESPONSIBILITIES:
- Create UVM/SystemVerilog based testbenches and tests.
- Make sure that design is bug free.
- Lead Formal verification.
- Support Post-Silicon teams for Product Performance, Power and functional issues debug/resolution
- Proficient in verification and testbench flows, especially seeking deep understanding and hands-on experience in System Verilog and UVM frameworks and testbenches, processes and flows.
- Proficient in the use of Linux-based tools and scripting in Perl, Python and Ruby.
